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4th February 2003

picoChip Designs announced it has sampled its first device, the PC101, which delivers a massive computational power of 30 Giga-MACs per second, twenty times more than traditional devices despite needing only a fraction of the clock rate (160MHz).

Shipped with a complete toolchain and a comprehensive UMTS systems library, the PC101 SSoC dramatically cuts the cost of third generation mobile infrastructure and enables the strategic advantage of in-the-field flexibility - a reprogrammable basestation.

The PC101 has a heterogeneous array of 430 16-bit processors on a single die interconnected by a fast deterministic fabric, delivering 200 Giga-instructions per second. The SSoC delivers the performance and efficiency of a conventional fixed function System on Chip but is completely programmable from standard C or assembler. The architecture was developed with a strong emphasis on ease of design/verification and deterministic performance for embedded signal processing - especially wireless and 3G. Complementing the device is a complete development tool-chain and a comprehensive systems library, providing a complete baseband platform for 3G infrastructure.

Co-Founder and CTO, Doug Pulley, said, "picoChip has overcome the design challenges of 0.13 um through architectural innovation and given our customers a viable alternative to the pains of SoC design. With the introduction of the picoArray, systems companies can place their own algorithms onto groups of processors in the same way as they would like to be able to place hardware IP blocks onto silicon in an ASIC - the Software System on Chip, or SSoC. In one device, users can integrate different processing tasks and algorithms, including DSP, protocol handling and control all using one consistent design environment and toolchain."

CEO, Dr. Rodger Sykes, added," We are proud of the PC101 - right first time 0.13um working silicon. We've implemented redundancy that provides very good yield despite the PC101's massive processing power. This provides our customers with a truly dramatic cost advantage compared to traditional approaches, delivering a compelling roadmap to the lowest cost/channel. As importantly, the tools and system library reduce development time and risk, accelerating time-to-market. Developing a 3G basestation can cost well over $100M - using our solution can reduce that significantly."

The PC101 is optimized for wireless communications tasks in two principal ways. At one level, the structure of the array and the arrangement of the different element types across the chip reflects the balance of requirements of a wireless system. Secondly, the characteristics and instruction set within processing elements varies according to their role, to include specialist operations or larger memory complements for control type operations.

Sean Lavey, an analyst from IDC, concludes, "Current WCDMA basestation designs are still not economic enough for mass deployment in the market. The need for flexibility in this evolving standard has made costly FPGAs the choice of most designs shipped over the past year, but we are now finding OEMs shifting most if not all of their baseband architectures to more cost effective flexible ASSP approaches. We expect this change will result in lower costs to the OEM sparking further cuts in pricing making WCDMA a more mainstream build-out issue for service providers over the next few years."