Multiple Bank Flash Memories for 3G Mobile Phones

STMicroelectronics has introduced a pair of multiple bank Flash memories targeted at high-performance next-generation mobile phones.

The 64-Mbit M58WR064ET and M58WR064EB are the first devices combining a multiple bank architecture, a 1.8V power supply voltage and a Synchronous Burst Read mode to increase the performance of more complex 3G mobile phones. Their development reflects ST's continuing commitment to meet the market's needs for advanced applications with innovative solutions.

Mario Licciardello, STMicroelectronics Flash Memories Division Director said: "These new parts are the result of ST's strong focus on developing dedicated Flash memories for mobile phones. Both devices combine advanced features with leading-edge technology and are expected to be among our most popular Flash memories over the next few quarters."

ST already offers a broad range of Flash memories, optimized for low-power, wireless systems and ideal for portable embedded applications, such as cellular phones, pagers and personal digital assistants (PDAs). The new M58WR064ET and M58WR064EB devices combine high density, low power consumption, greater programming throughput and smaller packages with high flexibility provided by the multiple bank architecture. All these features are essential for the mobile market.

The M58WR064ET and M58WR064EB feature an asymmetric block architecture. Each device contains 4-Mbit banks subdivided into a total of 135 blocks. There are 15 banks each containing eight main blocks of 32KWords, and one parameter bank containing eight parameter blocks of 4KWords and seven main blocks of 32KWords. The parameter blocks are at the top of the memory address space in the M58WR064ET, and at the bottom of the memory space in the M58WR064EB.

The bank architecture allows dual operations: while programming or erasing in one bank, Read operations are possible in the other bank. The multiple bank architecture of the M58WR064EB and M58WR064ET provides higher flexibility for dual operations since they can be performed on the basis of fifteen 4-Mbit banks. Both devices support Synchronous Burst Read and Asynchronous Read from all blocks of the memory array. At power-up the device is configured for Asynchronous Read. In Synchronous Burst mode, data is output on each clock cycle at frequencies of up to 54MHz. It is also possible to perform Burst Reads that cross bank boundaries.

The parts may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.65V to 2.2V VDD supply for the circuitry and a 1.65V to 3.3V VDDQ supply for the input/output pins. An optional 12V VPP power supply is provided to speed up customer programming. The M58WR064EB and the M58WR064ET have fast programming capabilities: Double and Quadruple Word Programming and Enhanced Factory Programming. The Double and Quadruple Word Program commands are used to program 2 and 4 adjacent words in parallel, respectively, while the Enhanced Factory Program command is used to program large streams of data within one block.

Each block can be erased separately. Erase can be suspended to program any other block, and then resumed. Programming can be suspended to read data from any other block, and then resumed. Each block can be programmed and erased over 100,000 times using the VDD supply voltage. There are two Enhanced Factory Program commands available to speed up programming.

The devices feature an automatic standby mode. During Asynchronous Read operations, they will automatically switch to the standby mode after a bus inactivity of 150ns. In this condition the power consumption is reduced and the outputs are still driven.

The parts are offered in a VFBGA56, 7.7 x 9mm, 0.75mm ball pitch package and are supplied with all the bits erased (set to '1').