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Broadcom Announces Industry's First Gigahertz Quad-Core Broadband Processor

4th October , 2004

US : Broadcom Corporation announced a new family of high performance, low power, integrated system-on-a-chip (SoC) processors targeted at data networking and communications applications, as well as security, storage, 3G wireless infrastructure, and high-density computing applications. Designed to incorporate the latest advances in chip multiprocessing (CMP) technology, the new Broadcom(R) broadband processors integrate up to four 64-bit MIPS(R) central processing unit (CPU) cores onto a single die. This innovation achieves much higher aggregate performance when compared with the use of multiple discrete cores while also dramatically reducing board space and power dissipation.

Chip multiprocessing is an advanced technique in CPU design that integrates two or more processor cores into a single chip to enhance computing performance. CMP scales system performance by sharing the workload across multiple cores, and relies on very high-speed on-chip interconnects and high bandwidth pipes to memory and input/output (I/O).

The other major benefit of CMP is power efficiency. The classic technique of scaling performance by increasing core frequency has reached the point of diminishing returns. Power and leakage have become a formidable challenge as designs become more complex with increasing numbers of transistors on a single die. The recent trend toward CMP is a clear recognition that a "power wall" exists, and that performance can only scale efficiently through the use of multi-core architectures.

According to IDC's "Worldwide Communication Processor and Network Processing Semiconductor 2003 Vendor Analysis," Broadcom achieved the largest communication processor market share gains in 2003 with its BCM1250 -- the embedded processor industry's first dual-core SoC -- and the BCM1125H, the embedded processor industry's first single-core processor with integrated HyperTransport(R) support. Today's announcement extends Broadcom's lead over other MIPS, PowerPC(R) and x86-based competitors who have yet to ship multi- core processors in volume.

"Over the past two years, Broadcom has achieved significant growth from its SB-1-based MIPS processors, especially within certain key communication infrastructure OEMs," said Sean Lavey, Program Manager at IDC. "This extension of its product line will take Broadcom's multi-core architecture to an even higher level of performance, enabling more OEMs across communications, storage, and other related embedded markets to start using multi-core processing solutions within their next generation designs."
"Broadcom's new dual- and quad-core processors build on the experience and success the company has gained with its dual-core BCM1250 processor," said Tom R. Halfhill, Senior Analyst at In-Stat/MDR. "The new processors leverage the proven SB-1 MIPS-compatible processor core optimized for networking and communications, and they will deliver even more processing power, memory and I/O bandwidth. They're also software compatible with the BCM1250 and the single-core BCM112x."

Broadcom's next generation products deliver up to 10,000 Dhrystone MIPS (million instructions per second), 32 billion floating-point operations per second (GFLOPS), 20 million packets per second of L3 forwarding performance, 100 Gigabit per second (Gbps) memory bandwidth, and up to 145 Gbps I/O bandwidth, all in a single-chip solution with power consumption of less than 25 Watts.

The new SoCs maximize the benefits of CMP architecture by integrating the processor cores with a multichannel 400 MHz double data rate 2 (DDR2) memory controller, four Gigabit Ethernet interfaces, a single 64-bit PCI-X interface running up to 133 MHz, and up to three 19.2 Gbps full duplex channels, all interconnected by a 256-bit wide high-speed internal bus. Symmetric multiprocessing (SMP), a key feature of Broadcom's multi-core architecture, takes this one step further by enabling all the cores to have access to the same shared pool of system resources, including memory and I/O.

"Broadcom revolutionized embedded processor design with the industry's first dual-core SoC," said David Kranzler, Senior Director of Broadcom's Broadband Processor Line of Business. "Broadcom once again raises the bar by demonstrating what CMP solutions can deliver in terms of performance, integration, power, scalability and design flexibility. Broadcom is committed to continually driving technical innovations in embedded processor design by working closely with our customers to understand their requirements and provide differentiated solutions."

Breakthrough Architecture Optimizes CPU, I/O and Memory Manufactured with 90nm CMOS process technology, Broadcom's new family of dual- and quad-core processors is based upon the field-proven multi-core architecture of the BCM1250, but provides substantially higher performance and scalability. The memory controller design is optimized not only for bandwidth, but also for efficient channel utilization. The controller supports DDR-400 and DDR2-800 for a peak bandwidth of 100 Gbps, enabling superior data plane forwarding performance. Configurable either as two 64-bit wide channels or four 32-bit wide channels for improved memory utilization, the memory controller supports up to 16 Gigabytes of memory with 1 Gigabit DRAM technology. The memory controller works closely with the on-chip L2 cache, scalable up to 1 Megabyte to provide a high performance memory system. The new SoC architecture also provides unparalleled I/O bandwidth and flexibility by integrating three independently configurable 19.2 Gbps I/O ports, which are connected to the processor cores via an on-chip, 256 Gbps cut-through switch. Each port can be configured by the customer to operate in SPI (Standard Packet Interface) 4.2 or 16-bit HyperTransport (HT) mode, running up to 600 MHz DDR. Broadcom's HyperTransport implementation is Rev 1.1 compliant, and enables not only memory and I/O traffic, but also packet traffic to be supported over the HT interface. The intelligent hash filter engine located in each of the ports enables classification and routing of all ingress traffic based on customer-programmable criteria; this feature is useful for a wide variety of applications from packet routing to load balancing.

For applications that can take advantage of distributed shared memory or coherent shared memory, ccNUMA (cache-coherent non-uniform memory access) support is provided to enable up to eight Broadcom chips, or 32 SB-1 CPU cores, to seamlessly communicate with each other over HyperTransport as if they were all cores on a single chip. This feature enables customers to design dense computing or processing clusters for performance scaling on a board or within a system.

The variety of standard and network I/O interfaces in the new Broadcom processor SoCs enables seamless connectivity to Broadcom CryptoNetX(TM) security processors, Broadcom ServerWorks(TM) I/O bridges and controllers, customer ASICs, network processors and other complementary chips.

Versatile for Embedded and High-Density Computing Applications Broadcom's broadband processors are ideal for scaling performance in networking applications such as routing and switching engines and blade servers for data centers; multi-function (e.g. intrusion detection, intrusion
prevention, anti-virus firewall, VPN) security appliances and/or chassis-based service blades; multi-protocol storage area network (SAN) switches, network attached storage (NAS) filers, and RAID arrays; and wireless infrastructure equipment such as radio network controllers (RNCs) and GPRS service and gateway nodes (GGSN/SGSN/PDSN).

For example, with the migration from 2/2.5G to 3G, wireless infrastructure platforms in core and radio access networks need to handle increasing traffic over time with additional throughput and protocol processing capacity. The quad-core processor provides the high compute performance and memory bandwidth required for protocol processing in the wireless core. In addition, the unique combination of superior arithmetic and floating- point (FP) performance of the SB-1 cores (up to 4.8 GFLOPS double-precision FP or 9.6 GFLOPS single-precision FP performance at 1.2 GHz per core), 100 Gbps memory bandwidth and low power achieved by the dual- and quad-core processors enables the new SoCs to significantly increase the performance density of computing applications. It also allows customers to pack more compute performance into a limited space and power envelope and reducing total system cost per FLOP.

Comprehensive Tools and Software Support
A complete suite of tools and software will be available for the new family of products, including Broadcom's production-quality Common Firmware Environment (CFE); debug tools from Corelis, Green Hills, and Viosoft; and support for multiple standard operating systems including VxWorks(R), Linux(R), OSE(R), Teja NP OS, and QNX(R). Additionally, application software including optimized TCP/IP and iSCSI stacks is available to maximize application performance and accelerate customers' time to market.

Availability and Pricing
Broadcom's new SiByte(R) family of 64-bit MIPS broadband processors includes the BCM1255, BCM1280, BCM1455 and BCM1480. The BCM1255, a dual-core processor, and the BCM1455, a quad-core processor, integrate the DDR2 memory controller as well as a single 64-bit PCI-X interface and four Gigabit Ethernet (GMII) interfaces. The BCM1280 dual-core and BCM1480 quad-core processors include all of these features plus three SPI-4/HT I/O ports for intelligent packet processing and routing, and multi-chip coherency support. The BCM1255 and BCM1280 are expected to sample in the fourth quarter of 2004. The BCM1455 and BCM1480 are expected to sample in the first quarter of 2005. Evaluation board platforms are expected to be available by the end of 2004.

Pricing for direct OEM customers for 10,000 piece quantities at 1 GHz starts from $599 each for the dual-core BCM12xx products and $999 each for the quad-core BCM14xx products.

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