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First
14-bit, Dual, 105 MSPS ADC Suitable for 3G |
| 2nd
October, 2006 |
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US : National Semiconductor unveiled the industry’s first 14-bit, dual, 1 GHz-input bandwidth analog-to-digital converter (ADC) with serial low-voltage differential signaling (LVDS) outputs for demanding communications, test and measurement, and imaging applications. At 105 mega-samples per second (MSPS), the ADC14DS105 heads a new family of 16 high-bandwidth, 12- and 14-bit ADCs. Designed with National’s unique low-power pipeline architecture on its 0.18u CMOS process technology, the ADC family’s high bandwidth performance enables excellent noise and distortion performance for 240 MHz and higher intermediate frequencies (IF). The ADC14DS105 provides a typical signal-to-noise ratio (SNR) of 72 dB and a spurious free dynamic range (SFDR) of 83 dB at a 240 MHz input frequency. This performance allows high intermediate-frequency (IF) sampling to eliminate an IF stage, relaxes filtering constraints and permits multi-carrier architectures. For third-generation (3G) communication receivers, designers can select 12-bit products to digitize one or two carriers, or 14-bit products to digitize three or four carriers requiring a higher dynamic range. The ADC family, with sample rates from 65 MSPS to 105 MSPS, features parallel CMOS or serial low-voltage differential signaling (LVDS) output options. The LVDS outputs reduce system noise while decreasing the number of input/output (I/O) pins and traces, enabling easier signal routing and flexible system partitioning. About the ADCs Part Number Bits
Speed Channels Outputs
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